1. Field of the Disclosure
The present disclosure relates to a poly crystalline silicon semiconductor device and a method of fabricating the same, and more particularly, to a poly crystalline silicon thin film transistor (TFT) and a method of fabricating the same for efficiently reducing the capacitance of gate bus lines.
2. Description of the Related Art
Poly crystalline silicon, which will be referred to as poly-Si hereafter, has characteristics of high mobility and excellent optical stability compared to amorphous silicon. Such poly-Si is used in various application fields, mainly in TFT and memory devices. Poly-Si TFTs are used as switching devices in displays. Examples of displays using an active device, such as TFTs, are TFT-LCDs and TFT-OLEDs.
In TFT-LCDs and TFT-OLEDs, TFTs are arranged in each pixel, which is arranged on an X-Y matrix. The performance of an LCD and an OLED in which a plurality of TFTs are arranged depends on the electric characteristics of the TFTs. One of the important characteristics of the TFT is the mobility of a silicon active layer. In order to improve the mobility of the silicon active layer, the silicon active layer should be crystallized. Studies of crystalline silicon are focused on the development of poly-Si, which is similar to mono crystalline silicon.
On the other hand, LCDs using plastic substrates, which are easily damaged by heat and flexible, unlike glass substrates, are being developed, in order to reduce the price of the LCD. In addition, a plastic substrate will be inevitably used in paper-like, flexible displays, which is a next-generation model.
However, the defect of plastic being easily damaged by heat requires a low temperature process to apply a plastic substrate to an LCD. Carry et al. disclosed a method of preventing damages on to plastic when forming silicon channels on a plastic substrate, in U.S. Pat. No. 5,817,550.
However, the method provided by Carry et al. results in a silicon film remaining, as an active region, under gates and as an unnecessary capacitive element under gate bus lines. The gate bus lines are formed with the gates, thus a gate insulating material and silicon for forming channels remain under the gate bus line.
This is because a gate metal is patterned, in other words, doped and activated, after depositing the gate insulating layer and the gate metal on the silicon and before patterning the channels. Thus, the silicon remaining on regions outside channel regions is not eliminated.
The silicon remaining under the gate bus lines and having a high dielectric constant generates an unnecessary parasitic capacitance between the gate bus lines and the substrate. In addition, the parasitic capacitance forms a line resistance of the gate bus lines and an RF differential circuit, thus distorts and delays the transfer of signals to the gates. Such a parasitic capacitance problem is generated in a semiconductor device having a plurality of transistors, for example, a CMOS.